1. Field of the Invention
The present invention relates generally to methods for fabricating gate electrodes, for use within devices such as but not limited to field effect transistor (FET) devices. More particularly, the present invention relates to methods for fabricating, with enhanced efficiency and enhanced performance, gate electrodes, for use within devices such as but not limited to field effect transistor (FET) devices.
2. Description of the Related Art
Semiconductor integrated circuit microelectronic fabrications are formed from semiconductor substrates within and upon which are formed semiconductor devices and over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
Common in the art of semiconductor integrated circuit microelectronic fabrication, as fabricated within semiconductor integrated circuit microelectronic fabrications, are field effect transistor (FET) devices. Field effect transistor (FET) devices as fabricated within semiconductor integrated circuit microelectronic fabrications are typically employed as switching devices within semiconductor integrated circuit microelectronic fabrications including but not limited to semiconductor integrated circuit microelectronic memory fabrications, semiconductor integrated circuit microelectronic logic fabrications and semiconductor integrated circuit microelectronic embedded memory and logic microelectronic fabrications.
While field effect transistor (FET) devices are thus desirable in the art of semiconductor integrated circuit microelectronic fabrication and often essential in the art of semiconductor integrated circuit microelectronic fabrication, field effect transistor (FET) devices are nonetheless not entirely without problems in the art of semiconductor integrated circuit microelectronic fabrication. In that regard, it is often difficult within the art of semiconductor integrated circuit microelectronic fabrication, and in particular within the art of complementary metal oxide semiconductor (CMOS) semiconductor integrated circuit microelectronic fabrication, to efficiently fabricate field effect transistor (FET) devices with enhanced performance.
It is thus desirable in the art of semiconductor integrated circuit microelectronic fabrication to provide methods for efficiently fabricating, with enhanced performance, field effect transistor (FET) devices within semiconductor integrated circuit microelectronic fabrications.
It is towards the foregoing object that the present invention is directed.
Various methods have been disclosed within the art of semiconductor integrated circuit microelectronic fabrication, for fabricating, with desirable properties, field effect transistor (FET) devices within semiconductor integrated circuit microelectronic fabrications.
Included among the methods, but not limited among the methods, are methods disclosed within: (1) Yu et al., in U.S. Pat. No. 6,218,234 (a method for integrating the fabrication of a polysilicon capacitor within a semiconductor integrated circuit microelectronic fabrication with the fabrication of a pair of field effect transistor (FET) devices within the semiconductor integrated circuit microelectronic fabrication); and (2) Cheek et al., in U.S. Pat. No. 6,261,885 (a method for fabricating, with controlled dopant diffusion effects, a pair of complementary metal oxide semiconductor (CMOS) field effect transistor (FET) devices within a semiconductor integrated circuit microelectronic fabrication).
Desirable in the art of semiconductor integrated circuit microelectronic fabrication are additional methods and materials which may be employed for fabricating, with enhanced performance, field effect transistor (FET) devices within semiconductor integrated circuit microelectronic fabrications.
It is towards the foregoing object that the present invention is directed.
A first object of the present invention is to provide a method for fabricating a field effect transistor (FET) device within a semiconductor integrated circuit microelectronic fabrication.
A second object of the present invention is to provide a method in accord with the first object of the present invention, wherein the field effect transistor (FET) device is efficiently fabricated, with enhanced performance, within the semiconductor integrated circuit microelectronic fabrication.
In accord with the objects of the present invention, there is provided by the present invention a method for fabricating a semiconductor integrated circuit microelectronic fabrication.
To practice the method of the present invention, there is first provided a semiconductor substrate having defined therein a first active region laterally adjacent a second active region. There is then formed over the first active region but not over the second active region a patterned first gate electrode material layer having formed aligned thereupon a first planarizing stop layer. There is then formed over the first planarizing stop layer and the second active region a blanket second gate electrode material layer. There is then planarized, while employing a planarizing method in conjunction with the planarizing stop layer, the blanket second gate electrode material layer to form therefrom a patterned second gate electrode material layer laterally adjacent but not over the patterned first gate electrode material layer. Finally, there is then further patterned the patterned first gate electrode material layer and the patterned second gate electrode material layer to form a corresponding first gate electrode over the first active region and a corresponding second gate electrode over the second active region.
The present invention provides a method for fabricating a field effect transistor (FET) device within a semiconductor integrated circuit microelectronic fabrication, wherein the field effect transistor (FET) device is efficiently fabricated, with enhanced performance, within the semiconductor integrated circuit microelectronic fabrication.
The present invention realizes the foregoing object by employing, in part, a planarizing method for forming, in a self aligned fashion, a patterned second gate electrode material layer laterally adjacent but not over a patterned first gate electrode material layer, such that upon further patterning of the patterned first gate electrode material layer and the patterned second gate electrode material layer there may be formed a first gate electrode over a first active region of a semiconductor substrate and a second gate electrode over a laterally adjacent second active region of the semiconductor substrate. Similarly, by employing the foregoing planarizing method in accord with the present invention, each of a blanket first gate electrode material layer from which is formed the patterned first gate electrode material layer and a blanket second gate electrode material layer from which is formed the patterned second gate electrode material layer may be formed employing an in-situ deposition dopant incorporation method, rather than an ion implantation dopant incorporation method, such as to provide for enhanced performance of a pair of field effect transistor (FET) devices within which are formed the first gate electrode and the second gate electrode.